High resolution imaging is closely related to the number of transistors and interconnections per pixel. Traditional voltage mode image sensors have been based on the three transistor (3T) active pixel sensor (APS) topology which has been coined by E. R. Fossum in “CMOS Image Sensor: Electronic Camera-On-A-Chip,” IEEE Trans. Electron Devices, Vol. 44, pp. 1689-1698, October 1997. The three transistor topology, which has been widely accepted as the industry standard, is composed of a reset transistor, switch transistor and a source follower (i.e., an active element that buffers the capacitance at the photodiode node from the large line capacitance). One of the drawbacks of the 3T APS are high dark currents and high temporal noise. In order to address these problems, a pinned photodiode was introduced as a part of a four transistor (4T) APS. (See, e.g., “A 0.6 μm CMOS pinned photodiode color imager technology,” Guidash, et al., Electron Devices Meeting, 1997. Technical Digest, International Dec. 7-10, 1997, Pages: 927-929.) The buried photodiode had lower dark current and the extra switch transistor allowed for truly correlated double sampling (CDS). The lower temporal noise variations have yielded impressive improvements in the signal to noise ratio, with staggering numbers of up to 60 dB. Unfortunately, the introduction of the extra switch transistor comes at a cost of larger pixel size and a lowering of the resolution of the image sensor.
In order to achieve high resolution voltage mode imaging, various pixel schemes have been published and they are summarized in Table 1. Y. Tida, et al. presented in “A ¼-Inch 330 k Square Pixel Progressive Scan CMOS Active Pixel Image Sensor,” IEEE J. Solid-State Circuits, v. 32, pp. 2042-2047, July 1994, two different pixel topologies in order to decrease the transistor count and interconnections per pixel. Both pixel topologies rely on capacitive addressing of the pixel resulting in low pixel sensitivity and increased spatial variations due to the increased capacitance at the photodiode node. In an article entitled “Single-Capacitor-Single-Contact Active Pixel,” Proc. IEEE ISCAS, Geneva, Switzerland, May 2000, Etienne-Cummings presented a single pixel with a single contact using a capacitive addressing scheme. However, large spatial variations, such as high fixed pattern noise, caused by gain variations of the in-pixel BJT, were one of the drawbacks of this implementation. In addition, various transistor sharing schemes on a neighborhood of pixels have been widely reported throughout the literature. In this case, four or eight 4T APS pixels share the reset and/or the read-out transistors among the four or eight pixels. This reduces the number of transistors per pixel to 1.75 or 1.25, respectively. (See Y. C. Kim, et al., “½ inch 7.2 mega-pixel CMOS image sensor with 2.25 μm pixel using 4-shared pixel structure for pixel-level charge summation,” in Digest. IEEE ISCCC, pp. 494-495, 2006; and S. Yoshihara, et al., “A 1/1.8-inch 6.4 Mpixel 60 fps CMOS Image Sensor with Seamless Mode Change,” in Digest. IEEE ISCCC, pp. 492-493, 2006.) Also, a small pitch, high fill factor image sensor was fabricated in a stack 3-D technology, where the photodiode was placed in a top tier and read out circuitry was placed in subsequent tiers, by J. Burns, et al., “A Wafer-Scale 3-D Circuit Integration Technology,” IEEE Trans. On Electron Devices, v. 53, pp. 2507-2516, October 2006. The stack 3-D fabrication technology has allowed for almost 100% fill factor since an entire tier is dedicated to the photodiode. Unfortunately, the shallow photodiode and high parasitic capacitance associated with intra-tier connections have had a direct impact on the poor sensitivity of the image sensor.
TABLE 1Summary of voltage mode active pixel sensors.Shared3TCapacitiveSingleSingle BJT4T APSPixel TypesAPS4T APSAddressTransistorPixel(1.75T)ReferenceFossumGuidashIida et. alIida et. alEtienne-Kim etet. alet al.Cummingsal.Transistors 34211 (BJT)7 (per 4per pixelpixels)Capacitors 0011 10per pixelInterconnections 56539 (per 4per pixelpixels)OutputvoltagevoltagevoltagevoltagevoltagevoltageFPN (%)0.1%0.1%averageaverage 3.5excellentSNR (dB)4545-60??3546.7Sensitivitygoodexcellentmediumpoorpoorexcellent
Current mode imaging has been a rival to the more traditional voltage mode APS, mentioned above. Current mode imaging techniques have spun a multitude of sensors, where visual information extraction at the focal plane has been the primary focus and a major strength of this technique. Conventional current mode imaging techniques are described by A. G. Andreou et al. in “A 48,000 pixel, 590,000 transistor silicon retina in current-mode subthreshold CMOS,” in Proc. 37th Midwest Symposium on Circuits and Systems, pp. 97-102, 1994; by T. Delbruck et al. in “Adaptive photoreceptor with wide dynamic range,” in Proc. IEEE Intl. Symp. on Circuits and Systems, pp. 339-342, 1994; by A. G. Andreou et al. in “Analog VLSI neuromorphic image acquisition and pre-processing systems,” Neural Networks, Vol. 8, No. 78, pp. 1323-1347, 1995; by K. A. Boahen et al. in “A retinomorphic vision systems,” IEEE Micro, Vol. 16, No. 5, pp. 30-39, October 1996; by S. Espejo et al. in “Switched-current techniques for image processing cellular neural networks in MOS VLSI,” Proc. IEEE Int. Symposium on Circuits and Systems, pp. 1537-1540, 1992; by R. Etienne-Cummings et al. in “A focal plane visual motion measurement sensor,” IEEE Trans. Circuits and Sys. I: Fundamental Theory and Applications, Vol. 44, No. 1, pp. 55-66, January 1997; by Eiichi Funatsu et al. in “An Artificial Retina Chip with Current-Mode Focal Plane Image Processing Functions,” IEEE Transactions on Electron Devices, Vol. 44, No. 10, October 1997; and by P. Dudek et al. in “A general-purpose processor-per-pixel analog SIMD vision chip,” IEEE Transactions on Circuits and Systems-I; Regular Papers, Vol. 52, No. 1, January 2005. The limiting factor in such current mode imaging sensors has been the low image quality due to the large fixed pattern noise (see Table 2).
TABLE 2Summary of current mode image sensors.QuadraticLinearLogarithmiccurrentcurrentPixel TypesPixelAPSAPSReferenceMead et. alPhillipet al.Transistorshighhigh3per pixelCapacitors0per pixelInterconnectionshighhigh5per pixelOutputcurrentFPN (%)>3%high0.5%SNR (dB)41 SensitivityexcellentExcellentgood
The primary contributor of fixed pattern noise in both voltage and current mode APS is the threshold voltage variations of the read-out transistor between pixels in the imaging array. As described by Fossum, in voltage mode APS, the linear voltage output with respect to the photodiode voltage coupled with correlated double sampling (CDS) circuits allows for suppression of threshold variations between readout transistors in the imaging array. In the current mode image sensor, the relationship between light intensity to output current can be logarithmic (see Delbruck et al.), quadratic (F. Boussaid, et al., “An ultra-low ower operating technique for mega-pixels current-mediated CMOS imagers,” IEEE Trans. on Consumer Electronics, v. 50, pp. 46-54, February 2004), or linear (see R. Etienne-Cummings, et al., “Neuromorphic vision systems for mobile applications,” in Proc. IEEE CICC. San Jose, Calif., 2006, San Jose, Calif.; and V. Gruev, et al., “Linear Current Mode Imager with Low Fix Pattern Noise,” Proc. IEEE ISCAS, Vancouver, Canada, May 2004). Due to the non-linear relationship between light and output current noted by Delbruck et al. versus Boussaid et al, canceling out voltage threshold variations is not easily performed on a chip. Linear photo current output with respect to photodiode voltage has been achieved by Etienne-Cummings, et al. and Gruev et al. by operating the read-out transistor of the pixel in linear mode. The linear current output coupled with current conveyers and current mode memory circuits has allowed for high read out speeds (high frame rates) and low fixed pattern noise (FPN) figures. However, one of the factors which has limited the linearity of the current output (hence impacting the FPN figure) has been the finite on-resistance of the access transistor in the pixel.
A current/voltage mode active pixel sensor is desired that overcomes the limitations of such prior art sensors and limits the size and number of transistors for each pixel so as to reduce resistance and to increase resolution. The present invention addresses this need in the art.